MIDI chip pinout

Statisitics
First some geeked out info which will only be of interest to other programmable logic freaks. As you can see the device is full up, but actually it can be optimised a little.

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
bpm           XC9536-15-PC44    36 /36  (100%) 45 /180 ( 25%)  7 /34  ( 20%)

Chip Pinout
One you have programmed the CPLD chip using your PC's parallel port it has these connections:

Device : XC9536-15-PC44


                  U                             
                  B                             
                  U                             
                  F                             
                  _                             
                  M        T     M              
                  I        E     I              
                  D        S     D     U        
                  I        T     I     N        
                  _        _     _     U        
               T  C  T  T  L  T  O  T  S  V  T  
               I  L  I  I  E  I  U  I  E  C  I  
               E  K  E  E  D  E  T  E  D  C  E  
               --------------------------------  
              /6  5  4  3  2  1  44 43 42 41 40 \
UBUF_SYS_CLK | 7                             39 | TIE
         TIE | 8                             38 | TIE
         TIE | 9                             37 | TIE
         GND | 10                            36 | TIE
         TIE | 11        XC9536-15-PC44      35 | TIE
         TIE | 12                            34 | TIE
         TIE | 13                            33 | TIE
         TIE | 14                            32 | VCC
         TDI | 15                            31 | GND
         TMS | 16                            30 | TDO
         TCK | 17                            29 | TIE
             \ 18 19 20 21 22 23 24 25 26 27 28 /
               --------------------------------  
               T  T  T  V  T  G  R  T  R  T  T  
               I  I  I  C  I  N  A  I  A  I  I  
               E  E  E  C  E  D  W  E  W  E  E  
                                 _     _        
                                 S     S        
                                 Y     Y        
                                 N     N        
                                 C     C        
                                 2     2        
                                 4     4        
                                 _     _        
                                 R     C        
                                 U     L        
                                 N     K        


Legend : TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin

Explanation
In (technical) English here's what the signals do:

MIDI_OUT: Logic level serial data output. You put this through some resistors to get the MIDI compatible signal
UNUSED: I used this as a test pin, now it does nothing
RAW_SYNC24_CLK: This is a signal from the first part of the circuit
RAW_SYNC24_RUN: This is another
UBUF_SYS_CLK: You connect a 1MHz clock to this
UBUF_MIDI_CLK: This internal signal is here for technical reasons due to the bizarre nature of Xilinx CPLDs
TEST_LED: You can connect an LED to this to verify that the chip isprogrammed
TDI, TDO, TCK, TMS: Signals used to program the chip

I designed the pinout so its possible to build the entire design on veroboard.

Back to main site